Services
Full-Stack ai
Engineering
One Team Across the EdgeAI Stack
By Doruk Sönmez, M.Sc.
AI Solutions Architect, CTai LABS/Connect Tech Inc.
Technical review: Rob Callaghan, P.Eng., Chief Product Officer, Connect Tech Inc.
Key Takeaways
- Full-stack ai engineering designs, integrates, optimizes, and deploys every layer of an Edge ai system, from silicon and carrier board through OS, BSP, sensor pipeline, model, and application interface, under one accountable team
- CTai LABS is structurally positioned for this: it’s a department of Connect Tech, the company that designs and manufactures the carrier boards the ai runs on
- The same organization that selects your Jetson module also wrote its BSP, engineered its thermal solution, integrated its camera buses, and optimized the model against its real power envelope
- That alignment across the stack is what prevents the handoff failures that break most Edge ai projects between pilot and production
CTai LABS brings full-stack ai engineering together under one roof as part of the CTI EdgeAI Stack, with ai architects, software developers, hardware and mechanical engineers, Support Application Engineers (SAEs), Field Application Engineers (FAEs), and in-house manufacturing working across the same development effort. That breadth gives customers access to engineering expertise from model and software development through compute, carrier design, thermal and mechanical integration, validation, and production. Third-party testing capabilities, long-standing relationships with key technology and vision partners, and Connect Tech’s decades of hardware and manufacturing experience further support the path from early development to deployable systems. With manufacturing in-house, CTai LABS can carry engineering decisions through to the physical system that is ultimately built, rather than handing the project off when development ends.
Why full-stack ownership is an engineering requirement, not a management preference
The Edge ai failure rate is not a model quality problem. Often, the failure is a systems integration problem, such as different teams owning different layers of the stack, and the gaps between those teams creating extra time-to-market on each layer and not working together.
Hardware and software integration failures often emerge at the interfaces between system components, making co-design across those layers an important engineering consideration (Edge AI and Vision Alliance, 2025). The causes are structural. When hardware selection, BSP development, sensor integration, and model optimization are handled by parties with no shared accountability, specific failure modes emerge that are predictable and preventable (Edge AI and Vision Alliance, 2025). Some issues include:
Hardware chosen after the model is trained
The power envelope, camera bus type, and thermal headroom of the target board are not confirmed before the model architecture is locked. Rework is expensive when the model does not fit the hardware it was never designed for.
BSP written by a party with no visibility into the board design
Timing issues, driver conflicts, and camera bring-up failures appear only after weeks of integration work, because the BSP author was not involved in the hardware design decisions.
Sensor data arriving wrong
Cameras, LiDAR, and IMUs integrated by a team that did not tune the model deliver data in a format the model was never trained on. Accuracy falls in the field.
Thermal reality ignored at design time
A model that runs on a workstation has to fit inside a 15-to-60-watt envelope, hold performance at 70 degrees ambient, and survive shock and vibration. None of that shows up in a cloud notebook.
Figure 1. Where fragmented ai engineering stalls at the Edge: gaps between separate hardware, BSP, sensor, and model teams.
The six layers CTai LABS owns and integrates
Full-stack ownership means owning the interfaces between layers, not just the layers themselves. Interface management is a core systems-engineering discipline because integration depends on maintaining compatibility across the products and subsystems that must work together (NASA, 2016).
Layer 1: Physical ai Hardware
Connect Tech designs and manufactures the carrier boards. For example, the Gauntlet board brings NVIDIA® Jetson Thor™ (T5000, Blackwell™ GPU, 2,070 FP4 TFLOPS) into a deployable form with 16-lane MIPI CSI-2, GMSL3/2/1, FPD-Link III, dual 10GbE, and CAN 2.0b. The Forge carrier board (AGX201) hosts Jetson AGX Orin™ with dual 10GbE, dual NVMe, and a -40C to +85C operating range in a 155 by 125 mm footprint. Hadron carries Jetson Orin™ NX and Jetson Orin™ Nano at around 23 grams with 9-to-60-volt input for UAV and SWaP-limited deployments. ThermiQ™ Edge ai cooling solutions are engineered for the same modules, so cooling is designed in from the first architecture review, not bolted on after a thermal failure in the field (Connect Tech, 2025).
Layer 2: Board Support Packages and operating systems
Connect Tech writes and maintains BSPs for its own carrier boards. The BSP is where hardware meets software: it includes the kernel, device tree, and drivers that expose the carrier’s full I/O to the operating system. Because CTai LABS is a department of Connect Tech, the same organization that made the hardware design decisions also owns the BSP. A BSP written without visibility into those hardware decisions is the most common source of camera bring-up failures, timing issues, and driver conflicts on third-party boards. That class of failure does not exist when the hardware and BSP come from the same organization.
Connect Tech BSPs are typically built on NVIDIA JetPack SDK and validated against each new SDK release (NVIDIA, 2025b). The same team maintains BSP continuity across the product lifecycle, which is the basis for long-term production support.
Layer 3: NVIDIA software stack
Through Connect Tech’s NVIDIA Elite Partner standing, the highest status level, CTai LABS builds on NVIDIA TensorRT™ for optimized inference, NVIDIA Isaac ROS for accelerated perception, navigation, and sensor fusion, JetPack SDK for the full platform stack, DeepStream for video analytics, and Holoscan for medical and high-frequency sensor applications. These are not configured in isolation. They are configured against the specific carrier board, BSP, and thermal solution the project is running on.
Layer 4: Physical ai Sensor integration
Cameras across MIPI CSI-2, GMSL2/3, and FPD-Link III, plus LiDAR, IMUs, radar, and CAN peripherals, are brought up by the same team that will optimize the model against the data they produce. End-to-end integration means sensor timing, data format, and pipeline latency are resolved before the model sees production data.
Camera bring-up on GMSL2/3 and FPD-Link III is a BSP-level task. A software team working from a third-party carrier cannot resolve the bring-up issues that originate in the carrier board design. CTai LABS can, because the carrier board design is in-house.
Layer 5: Edge ai Model optimization and validation
TensorRT conversion and INT8/FP16 quantization run on the actual target board in the actual power mode. Not a desktop workstation. Not a development kit. The board, the BSP, the sensor pipeline, and the model are all present at optimization time, which is when the real performance figures are set.
Validation runs through three stages: Software-in-the-Loop (SIL), Hardware-in-the-Loop (HIL), and Digital Twin testing in NVIDIA Omniverseâ„¢ Isaac Simâ„¢. Validation records are produced as program documentation deliverables.
Layer 6: Application interface and production support
The deployment-ready handoff includes a RESTful API layer where the system connects to external infrastructure, documented hardware and software configuration, and OTA update architecture for fleet deployment. Production support is backed by Connect Tech’s BSP and software teams, the same team that built the system.
Figure 2. The CTai LABS full-stack ai engineering layer model: every layer from hardware to application interface, owned by one team.
Platform selection: Orin vs. Thor and the Connect Tech carrier board lineup
The hardware decision determines what is possible in every layer above it. CTai LABS makes that decision against actual project constraints: compute workload, power envelope, camera bus type, sensor count, physical size, ingress rating, and long-term module availability.
Platform selection: Orin vs. Thor and the Connect Tech carrier board lineup
| Capability | Jetson AGX Orin | Jetson Thor (T5000) |
|---|---|---|
| GPU architecture | NVIDIA Ampere, 2,048 CUDA cores | NVIDIA Blackwell, 2,560 CUDA cores, 5th-generation Tensor cores |
| ai compute | Up to 275 TOPS (INT8) | 2,070 FP4 TFLOPS / 1,035 FP8 TFLOPS |
| Memory | 64 GB LPDDR5, 204.8 GB/s | 128 GB LPDDR5X, ~273 GB/s |
| MIG (Multi-Instance GPU) | Not supported | Up to 2 isolated GPU instances |
| FP4 inference | Not supported | Native FP4 Transformer Engine |
| Best full-stack role | Industrial vision, logistics AMRs, and defense payloads | Humanoids, multi-model autonomy, and VLA model deployment |
Note: Jetson Thor’s 2,070 FP4 TFLOPS figure is measured at FP4 precision on the Blackwell architecture and is not directly comparable to Jetson Orin’s 275 TOPS at INT8. Jetson Thor delivers approximately 7.5 times the ai compute and 3.5 times the energy efficiency of Jetson AGX Orin at the compute-per-watt level (NVIDIA, 2025c). MIG support on Jetson T5000 allows the GPU to be partitioned into two physically separated GPU instances, providing workload isolation on a single module.
Connect Tech carrier selection
Platform selection means choosing the module and the carrier together. The carrier determines I/O, thermal design, form factor, ingress rating, and long-term availability. The table below maps common full-stack deployment scenarios to Connect Tech solutions (Connect Tech, 2025).
| Connect Tech Platform | NVIDIA Module | Compute | Key I/O for full-stack integration | Environment |
|---|---|---|---|---|
| Gauntlet | Jetson Thor (T5000) | 2,070 FP4 TFLOPS · 40–130 W | 16-lane MIPI CSI-2, GMSL3/2/1, FPD-Link III, 2× 10GbE, CAN 2.0b, 2× NVMe | Rugged, deployable |
| Forge (AGX201) | Jetson AGX Orin | Up to 275 TOPS · 15–60 W | 2× 10GbE + 2× GbE, 2× NVMe M.2, DisplayPort, MIPI CSI-2 | 155 × 125 mm, -40°C to +85°C |
| Rogue-RX (AGX203) | Jetson AGX Orin Industrial | Up to 248 TOPS · 15–75 W | Positive-lock connectors, wide input voltage, 2× 10GbE, 16-lane MIPI CSI-2 | Ruggedized, -40°C to +85°C |
| Hadron / Super Hadron | Jetson Orin NX / Nano | Up to 157 TOPS (Super Mode) | GMSL coax camera, 9–60 V input, headless operation | ~23 g, UAV-ready |
| Boson / Lepton | Jetson Orin NX / Nano | Up to 157 TOPS (Super Mode) | FPD-Link III, CAN FD, on-board deserializers | Compact, multi-camera |
| Anvil-T5 | Jetson Thor (T5000) | 2,070 FP4 TFLOPS · 40–130 W | GMSL3/2, FPD-Link III, SDI, active cooling to 60°C | Full system, rugged |
Note: Rogue-RX is part number AGX203. Rogue-RX XP (AGX207) is a separate product with an extended power input range. Boson part number should be confirmed with CTI before specification. ThermiQâ„¢ passive and active cooling is available across the full Orin and Thor module range (Connect Tech, 2025).
Figure 3. Example Connect Tech solutions for full-stack ai engineering, mapped by compute tier.
What full-stack engineering actually changes
Two deployments of the same Jetson module with the same model can perform very differently depending on who owns the layers underneath. Full-stack ownership changes specific, measurable outcomes:
Camera bring-up
GMSL2/3 and FPD-Link III camera integration can involve the carrier hardware, BSP, drivers, and sensor configuration. When the carrier and BSP are developed within the same organization, hardware- and software-level issues can be investigated without an additional vendor handoff.
Inference performance at real power limits
Model optimization on the target hardware allows performance, power mode, and thermal behavior to be evaluated under the conditions intended for deployment. This gives the engineering team a more representative basis for optimization than workstation-only testing.
Sensor-to-model consistency
Developing the sensor pipeline and model within the same project context allows data formats, preprocessing, timing, and sensor characteristics to be considered during model development and integration.
Integration timeline
Handoffs between hardware vendors, BSP teams, and software integrators introduce coordination latency. Single-team ownership removes those handoffs. The connection between Connect Tech’s hardware design and BSP development teams allows carrier-level and software-level issues to be addressed within the same organization.
Physical Robotics Proof point: Data. Analytics. Vision. Execution. (D.A.V.E.)
D.A.V.E. (Data. Analytics. Vision. Execution.) is one of Connect Tech’s in-house autonomous mobile robots, built, and operated on Connect Tech Edge hardware by the CTai LABS team. Every layer described above, hardware, BSP, NVIDIA software stack, sensor integration, model optimization, is running on D.A.V.E. in a real physical system, not a lab rack or a simulation.
For a full-stack ai engineering firm, testing its own deployed systems is the most direct form of validation. The integration problems that appear in customer projects appear on D.A.V.E. first. The team knows where those problems are before your project reaches them.
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ABOUT THE AUTHOR
Doruk Sönmez, M.Sc.
AI Solutions Architect, CTai LABS
Doruk is an AI Solutions Architect at CTai LABS, the Physical AI and Edge AI services division of Connect Tech Inc., an NVIDIA Elite Partner. An NVIDIA DLI Certified Instructor, he specializes in deploying vision-language models, agentic AI workflows, and accelerated video pipelines on NVIDIA Jetson platforms.
Learn More
Resources and Frequently Asked Questions
Related
Sources
Connect Tech. (2025). Gauntlet carrier board for NVIDIA Jetson Thor; Forge carrier board (AGX201); Rogue carrier board (AGX202); Rogue-RX carrier board (AGX203); Anvil-T5 (ESG625); Hadron and Super Hadron carriers; Boson and Lepton carriers; ThermiQ thermal solutions [Product documentation].
https://connecttech.comEdge AI and Vision Alliance. (2025, August 8). The $2.4 trillion crisis: Why hardware/software integration is your most critical technical decision.
https://www.edge-ai-vision.com/2025/08/the-2-4-trillion-crisis-why-hardware-software-integration-is-your-most-critical-technical-decision/National Aeronautics and Space Administration. (2016). NASA systems engineering handbook (NASA/SP-2016-6105 Rev2).
https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/20170001761.pdfNVIDIA. (2025a). Jetson AGX Orin: Performance specifications.
https://www.nvidia.com/en-us/autonomous-machines/embedded-systems/jetson-orin/NVIDIA. (2025b). Jetson Linux (L4T): BSP, kernel, and drivers for NVIDIA Jetson modules.
https://developer.nvidia.com/embedded/linux-tegraNVIDIA. (2025c). Jetson Thor: Advanced ai for physical robotics.
https://www.nvidia.com/en-us/autonomous-machines/embedded-systems/jetson-thor/Frequently Asked Questions
What does full-stack ai engineering cover?
Every layer of an Edge ai system under one team: hardware selection and design, board support package and bring-up, NVIDIA software stack configuration (TensorRT, Isaac ROS, JetPack, DeepStream, Holoscan), sensor integration, model optimization and quantization, SIL/HIL/Digital Twin validation, deployment-ready handoff, and production support. The point is that no layer is handed off to a separate party.
How is full-stack ai engineering different from systems integration?
A systems integrator assembles components from third-party vendors and manages the interfaces between them. Full-stack ai engineering means owning the components as well as the interfaces, specifically the hardware itself. CTai LABS is a department of Connect Tech, which manufactures the carrier boards. Connect Tech, which also designed and manufactured the carrier, wrote its BSP. CTai LABS, as a department of Connect Tech, brings that BSP ownership into every engagement. That is not a coordination difference. It is an engineering depth difference.
Why does BSP ownership matter so much?
The BSP is the layer where hardware meets software. Camera bring-up failures, timing issues, and driver conflicts are resolved at the BSP level. A team working from third-party hardware cannot resolve those issues at the source because they have no visibility into the hardware design decisions. CTai LABS is a department of Connect Tech, which means the carrier board design and the BSP both come from the same organization. When a BSP-level issue appears, it gets resolved by the team that made the board, not escalated to a third party.
What is the engineering case for Jetson Thor over Jetson AGX Orin?
Jetson Thor on the Blackwell architecture brings three capabilities Jetson AGX Orin does not have: native FP4 inference via the Transformer Engine, Multi-Instance GPU (MIG) for deterministic multi-workload execution, and approximately 7.5 times the ai compute at 3.5 times the energy efficiency. For multi-model, generative, or vision-language-action model workloads, Jetson AGX Orin is the compute bottleneck. For most industrial vision and logistics AMR applications, Jetson AGX Orin is sufficient.
How does ThermiQ thermal design connect to model performance?
Thermal envelope sets the ceiling for the power mode, and power mode sets the ceiling for sustained inference performance. A model that was optimized at a power mode the platform cannot sustain in the field will throttle. ThermiQ cooling is selected and configured at the same time as the module and power mode, so the model is optimized against what the system can actually maintain at operating temperature.
What is Multi-Instance GPU (MIG) and when does it matter?
MIG is a Jetson Thor capability that allows the GPU to be partitioned into up to two isolated GPU instances, each with its own memory and compute resources. It matters for humanoid robotics and advanced AMR applications where multiple models must run concurrently without competing for GPU resources.
Can CTai LABS work with a model already developed in-house?
Yes. The team takes existing models through TensorRT conversion and quantization on the actual target hardware, integrates them with Isaac ROS where perception and navigation are involved, and validates them against the full production sensor pipeline. The starting point can be a trained model, a dataset, or a use-case definition.
What is the typical path from Jetson AGX Orin to Jetson Thor for existing deployments?
Rogue (AGX202) users migrate to Rogue-T5 (AGX302). Rogue-RX (AGX203) users have a similar path. Anvil (ESG620) users migrate to Anvil-T5 (ESG625). Forge (AGX201) users move to Gauntlet (AGX301) as the closest Jetson Thor equivalent in form factor and I/O. Application-level code ports with minimal changes; TensorRT engines must be rebuilt for Blackwell. The Jetson Orin vs. Jetson Thor resource covers the full migration framework.
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